TSM-12: RELIGN: A Homoiconic Language for Synchronous, Stateful Reactive Hardware Design

As the inventor of Verilog, give a keynote at DAC about an ideal hardware design language based on TBC and Hexons that combines the syncronicity of SIGNAL with the statefulness of Erlang.ChatGPT Prompt (condensed) Opening: Setting the Stage Phil Good morning, everyone. It’s great to be here at DAC—a conference that brings together the best... Continue Reading →

December 2, 2024 0

TSM-10.2: HLIR NextGen – A TableGen Replacement for MLIR

The HLIR (High-Level Intermediate Representation) framework written in Homoiconic C could also serve as a next-generation replacement (“HLIR-NG”) for LLVM’s TableGen, especially if it’s designed to handle the kind of semantic richness and extensibility required for a dynamic, multi-level execution framework like MLIR.

November 30, 2024 0

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